System Verilog, OVM, UVM rant and thoughts

If you have ever done any work with OVM/UVM or System Verilog, you will quickly realize that the online resources for them are almost non-existent, compared to the likes of Python, NodeJs and all their associated web frameworks that is all the rage now. The ones that do exists are really old and in most cases does not do a good job of explaining... Read more 15 Dec 2018 - 1 minute read

Euler Project - Problem 2

Attempt at problem 2. Not my first rodeo, but enjoyable regardless. Read more 14 Dec 2018 - 1 minute read

Euler Project - Problem 1

Restarting my journey to solve the problems in https://projecteuler.net/ This will be the very first. Read more 14 Dec 2018 - 2 minute read

New Layout - Lagrange

Finally got the motivation to come back and do some updates to this blog. I can’t believe it. It has actually been two years since I last updated! As you can see, I have opted into using this minimalistic Lagrange theme. Read more 12 Dec 2018 - less than 1 minute read

Real-time Image Filtering using FPGA

During my undergraduate years in Penn State, one of the project I have worked on is using FPGA to do an image processing at real time. The goal of the project was to feed in video stream from a camera and be able to do edge filtering with it at real time. My motivation for this project was two fold: one, I’ve read some articles online that there... Read more 30 Dec 2017 - 4 minute read